Some uses of electrically programmable memories are highly constrained in terms of available space, as in the case for cards incorporating microprocessors, also called smart cards, or any integrated-circuit device on a semiconductor wafer. In addition, in contactless smart card applications, for example, little power may be available because such smart cards generally do not have an internal power supply and are powered remotely by an external reader. In this sort of application, low power consumption may be a second constraint.
In these applications, it is common to use flash memories, which have the advantage of a very simple and compact structure, providing a large storage capacity with a small footprint. However, programming these flash memories may require substantial voltages, which induce large leakage currents and overall high power consumption. Thus, these memories may fail to meet some requirements.
Actual flash memories are produced using metal oxide semiconductor (MOS) transistors. Programming of such transistors takes place in the presence of a high drain-source current and makes use of a mechanism for injecting electrical charge into the floating gate called “hot carrier injection.” In contrast, the memory is erased by a tunneling effect (Fowler-Nordheim tunneling) by applying, to the transistors, voltages that extract the charge trapped in the floating gate, with a negligible flow of current between the drain and the source.
The typical hot-carrier-injection transistor has low injection efficiency, and may require a high programming current of about 50 μA per transistor. This property limits the number of transistors that can be programmed simultaneously in a memory, this number generally being equal to 8, 16, or 32 transistors. In low-consumption semiconductor products, the number of transistors that can be simultaneously programmed is furthermore limited by power-consumption constraints. Currently available approaches do not satisfactorily address these problems.
FIG. 1 is a cross-sectional view of a typical structure of a hot-electron-injection MOS transistor 10 comprising nanocrystals. This transistor 10 comprises a p-type substrate 1, n-type source (S) and drain (D) regions (2 and 3, respectively), a floating gate 8 made of a dielectric 11 in which electrically conductive nanoparticles 12 have been incorporated, for example, silicon or germanium nanocrystals, and a control gate 4. Each nanoparticle may act as an independent floating gate and is able to trap electrons. In the following, the expression “floating gate” will be used to denote the layer comprising all the nanocrystals of such a transistor. The control gate 4 is generally made of polysilicon (polycrystalline silicon). The control gate 4 and the source 2 and drain 3 regions are provided with electrical contacts, shown schematically. The floating gate 8 is electrically insulated from the substrate 1 and the control gate 4 by the dielectric 11. The conductive particles 12 of the floating gate 8 may accumulate electrical charge that modifies the threshold voltage of the transistor.
The transistor 10 is programmed by applying a positive voltage VD to the drain region 3, a positive voltage VCG to the control gate 4, a zero voltage VS (ground or GND) to the source region 2, and a zero or negative voltage to the substrate, these voltages being chosen so as to place the transistor into a saturated operating mode. The gate voltage VCG generates a vertical electric field EV. The electric field EV causes an inversion zone 5 to appear in the substrate 1, forming an n-type conductive channel in which electrons can flow and which has a pinch-off zone 6 neighboring the drain region 3. The drain-source potential difference generates a current IDS, between the drain region 3 and the source region 2, corresponding to a stream of electrons flowing in the opposite direction between the source region 2 and the drain region 3. At the pinch-off zone 6, the electrons have a high kinetic energy, thereby generating hot carriers, some of which overcome the potential barrier of the dielectric material 11 and penetrate into the nanocrystal zones 12 of the floating gate 8 where they remain trapped locally. The substrate region 1 lying between the pinch-off zone 6 and the drain region 3 is thus called the injection zone 7.
The electrical charge trapped in the nanocrystals of the floating gate 8 modifies the threshold voltage of the transistor. This threshold voltage may then be measured by a read amplifier that delivers as output a 0 or 1 logic value depending on whether the transistor is in the programmed state, i.e. electrons are present in the floating gate, or not (the unprogrammed state being called the erased state).
As indicated above, such a transistor structure 10 has a low injection efficiency, i.e. the ratio of the current IDS that flows during programming to the current that is injected into the nanocrystals, is low (the amount of electrical charge trapped being equal to the current injected multiplied by the injection time).
This low efficiency is a result of the vertical electric field EV being greatly attenuated near the injection zone 7. The field strength is high near the source region 2, but is gradually attenuated as it approaches the drain region 3 because it is neutralized by the drain voltage VD, thereby also causing pinch-off 6 of the channel.
Production of such a transistor generally comprises first producing an insulating layer, generally a silicon oxide layer, then depositing conductive nanoparticles, generally silicon nanocrystals, and then depositing a dielectric layer on the nanocrystals, which may be an oxide or an oxide/nitride/oxide trilayer. Next, a step of depositing and etching polycrystalline silicon allows the control gate 4 of the transistor to be formed. This gate then acts as a mask for forming the drain and source regions of the transistor.